module booth(
iclk, // input clock
iReset, // reset signal
iReady, // indicates inputs are ready
oDone, // indicates that the result is ready
iMultiplier, // 8-bit multiplier [7:0]
iMultiplicand, // 8-bit multiplicand [7:0]
oProduct // 16-bit product [15:0]
);




input [7:0] iMultiplier, iMultiplicand;
input iclk, iReset, iReady;
output [7:0] oDone;
output [15:0] oProduct;
assign wire [7:0] A;
assign wire [7:0] a;
assign wire [7:0] L;
assign wire [7:0] l;
assign wire [7:0] o;
assign wire [16:0] p;
assign wire [16:0] P;
assign wire [16:0] op;
assign wire [16:0] OP;
assign wire Q;
assign wire q;
assign wire [7:0] muxout;

d_ff A0(a[0], A[0], iReset, iclk);
d_ff A1(a[1], A[1], iReset, iclk);
d_ff A2(a[2], A[2], iReset, iclk);
d_ff A3(a[3], A[3], iReset, iclk);
d_ff A4(a[4], A[4], iReset, iclk);
d_ff A5(a[5], A[5], iReset, iclk);
d_ff A6(a[6], A[6], iReset, iclk);
d_ff A7(a[7], A[7], iReset, iclk);

d_ff L0(l[0], L[0], iReset, iclk);
d_ff L1(l[1], L[1], iReset, iclk);
d_ff L2(l[2], L[2], iReset, iclk);
d_ff L3(l[3], L[3], iReset, iclk);
d_ff L4(l[4], L[4], iReset, iclk);
d_ff L5(l[5], L[5], iReset, iclk);
d_ff L6(l[6], L[6], iReset, iclk);
d_ff L7(l[7], L[7], iReset, iclk);

d_ff o0(o[0], oDone[0], iReset, iclk);
d_ff o1(o[1], oDone[1], iReset, iclk);
d_ff o2(o[2], oDone[2], iReset, iclk);
d_ff o3(o[3], oDone[3], iReset, iclk);
d_ff o4(o[4], oDone[4], iReset, iclk);
d_ff o5(o[5], oDone[5], iReset, iclk);
d_ff o6(o[6], oDone[6], iReset, iclk);
d_ff o7(o[7], oDone[7], iReset, iclk);

d_ff q0(q, Q, iReset, iclk);

d_ff P0(p[0], P[0], iReset, iclk);
d_ff P1(p[1], P[1], iReset, iclk);
d_ff P2(p[2], P[2], iReset, iclk);
d_ff P3(p[3], P[3], iReset, iclk);
d_ff P4(p[4], P[4], iReset, iclk);
d_ff P5(p[5], P[5], iReset, iclk);
d_ff P6(p[6], P[6], iReset, iclk);
d_ff P7(p[7], P[7], iReset, iclk);
d_ff P8(p[8], P[8], iReset, iclk);
d_ff P9(p[9], P[9], iReset, iclk);
d_ff P10(p[10], P[10], iReset, iclk);
d_ff P11(p[11], P[11], iReset, iclk);
d_ff P12(p[12], P[12], iReset, iclk);
d_ff P13(p[13], P[13], iReset, iclk);
d_ff P14(p[14], P[14], iReset, iclk);
d_ff P15(p[15], P[15], iReset, iclk);
d_ff P16(p[16], P[16], iReset, iclk);

d_ff OP0(op[0], OP[0], iReset, iclk);
d_ff OP1(op[1], OP[1], iReset, iclk);
d_ff OP2(op[2], OP[2], iReset, iclk);
d_ff OP3(op[3], OP[3], iReset, iclk);
d_ff OP4(op[4], OP[4], iReset, iclk);
d_ff OP5(op[5], OP[5], iReset, iclk);
d_ff OP6(op[6], OP[6], iReset, iclk);
d_ff OP7(op[7], OP[7], iReset, iclk);
d_ff OP8(op[8], OP[8], iReset, iclk);
d_ff OP9(op[9], OP[9], iReset, iclk);
d_ff OP10(op[10], OP[10], iReset, iclk);
d_ff OP11(op[11], OP[11], iReset, iclk);
d_ff OP12(op[12], OP[12], iReset, iclk);
d_ff OP13(op[13], OP[13], iReset, iclk);
d_ff OP14(op[14], OP[14], iReset, iclk);
d_ff OP15(op[15], OP[15], iReset, iclk);


initial begin

l[7:0] = iMultiplier[7:0];
oDone[7:0] = 8'b10000000;
end

ALU3 alu1(A[7:0],iMultiplicand[7:0],{Q,L[0]},iclk,muxout[7:0]);
 
always @(posedge iclk) begin
p[16:9] = muxout[7:0];
p[8:1] = L[7:0];
op[14:0] = P[16:2];
op[15] = 1'b 0;
a[7:0] = OP[15:8];
l[7:0] = OP[7:0];
o[6:0] = oDone[7:1];

end

endmodule
